Verilog Tutorial

A nice tutorial for Verilog can be found here. It uses Icarus Verilog to do simulation and compilation. The focus of this post is to show you the importance of the command line and the variation of its commands.

Compiler Option for Icarus iverilog

command

iverilog [−ESVv] [−Bpath] [−ccmdfile|−fcmdfile] [−Dmacro[=defn]] [−pflag=value] [−dname]
[−g1995|−g2001|−g2005|−g] [−Iincludedir] [−mmodule] [−Mfile] [−Nfile] [−ooutputfilename]
[−stopmodule] [−ttype] [−Tmin/typ/max] [−Wclass] [−ypath] sourcefile

DESCRIPTION of the command
 
The command  generates vvp file for simulation, but can also be used for  synthesis. 

OPTIONS

iverilog accepts a huge lot of  options. It is beyond the scope of this document to discuss all that. 

If you are instead looking for FPGA implementation you may like to take a look at the Verilog Tutorial for Xilinx ISE.